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  • 70 Comments
Joined 5 months ago
Cake day: June 3rd, 2024
  • ms.lane@lemmy.worldtoTechnology@lemmy.world•Intel says integrating RAM into Lunar Lake SoC was a mistake, might abandon desktop GPUs againEnglish
    81·
    1 day ago

    Intel realized it back then too, but things didn’t pan out the way they wanted.

    nVidia and AMD were going to merge while ATi was circling the drain. Then Jensen and Hector Ruiz got into their shitfight about who was going to be CEO of the marged AMD/nVidia (it should have been Jensen, Hector Ruiz is an idiot) which eventually terminated the merger.

    AMD, desperately needing a GPU side for their ‘future is fusion’ plans, bought the ailing ATi at a massive premium.

    Intel was waiting for ATi to circle the drain a little more before swooping in and buying them cheap, AMD beat them to it.

  • ms.lane@lemmy.worldtoGames@lemmy.world•Whatever happened to racing gamesEnglish
    3·
    6 days ago

    Do you want themed racing games in different time periods?

    If you’re using realworld(or alikes) cars, there isn’t really much more to go for, you’ve got circuit, street, rally, drift and touring cars - which really the only thing you can start to really differ is locale or time period.

    F1 is F1 and F1 fans will slaughter anyone who tries to mess with F1. But also there are yearly games, since the rules change every year and the new game is the new rules.

    Do you want more arcade style?

    What are the indie games that have piqued your interest?

  • ms.lane@lemmy.worldtoTechnology@lemmy.ml•Intel, AMD CPUs on Linux impacted by newly disclosed Spectre bypassEnglish
    1·
    15 days ago

    The only way to do that is to completely disable Out-of-order execution to begin with and disable any shared caches, which would completely neuter modern CPUs. Not a little bit, that’s going to be around ~30% of the prior performance - not a 30% loss, a 70% loss…

    From ChatGPT- (query: How much performance would a modern Zen 5 or Intel Alder Lake CPU lose if you completely stripped out/disabled SMT, Out of Order Execution and shared caches - operating in-order and only using dedicated (non-shared) caches?)

    Stripping out or disabling key performance-enhancing features like Simultaneous Multithreading (SMT), Out-of-Order Execution (OoOE), and shared caches from a modern CPU based on architectures like AMD’s Zen 5 or Intel’s Alder Lake would result in a significant performance loss. Here’s an overview of the potential impact from disabling each feature:

    1. Simultaneous Multithreading (SMT)

      Impact: SMT allows a single core to execute multiple threads simultaneously, improving CPU throughput, especially in multi-threaded applications. Disabling SMT would reduce the ability to handle multiple threads per core, decreasing performance for multi-threaded workloads. Expected Loss: Performance drop can be around 20-30% in workloads like video encoding, rendering, and heavily threaded applications. However, single-threaded performance would remain relatively unaffected.

    2. Out-of-Order Execution (OoOE)

      Impact: OoOE allows the CPU to execute instructions as resources become available, rather than in strict program order, maximizing utilization of execution units. Disabling OoOE forces the CPU to operate in-order, meaning that it would stall frequently when waiting for data dependencies or slower operations, like memory access. Expected Loss: This could lead to performance drops of 50% or more in general-purpose workloads because modern software is optimized for OoOE processors. Tasks like complex branching, memory latency hiding, and speculative execution would suffer greatly.

    3. Shared Caches (L2, L3)

      Impact: Shared caches (particularly L3 caches) help reduce memory latency by sharing frequently accessed data among multiple cores. Disabling shared caches would increase memory access latency, causing more frequent trips to slower main memory. Expected Loss: Performance could drop by 15-30% depending on the workload, especially for applications that benefit from high cache locality, such as database operations, scientific simulations, and gaming.

    4. Operating In-Order Only with Dedicated Caches

      Overall Impact: Without OoOE and SMT, and with only in-order execution and dedicated caches, the CPU would be much less efficient at handling multiple tasks and hiding latency. Modern CPUs rely heavily on OoOE to keep execution units busy while waiting for slow memory operations, so forcing in-order execution would significantly stall the CPU. Expected Loss: Depending on the workload, the overall performance degradation could be upwards of 70-80%. Some specialized applications that rely on high parallelism and efficient cache usage might perform even worse.

    Summary of Overall Performance Impact:

    • Single-threaded tasks: May see performance drop by 50-70% depending on reliance on OoOE and cache efficiency.

    • Multi-threaded tasks: Could experience a combined drop of 70-80%, as the lack of SMT, OoOE, and shared caches compound the inefficiencies.

    This hypothetical CPU configuration would essentially mimic designs seen in early microprocessors or microcontrollers, sacrificing the massive parallelism, latency hiding, and overall efficiency that modern architectures provide. The performance would be more in line with processors from a couple of decades ago, despite the higher clock speeds and core counts.

    Case in point, it’s not feasible, if you’re looking for that in your own computer, you can do it already. I doubt anyone will follow you though.